ONF Connect 2019

RISC-V is a free and open instruction set architecture defined through open standards-based collaboration.  The Chips Alliance organization was created recently to host open source implementations of hardware IP blocks, including RISC-V based cores.  We expect the RISC-V ecosystem to change the landscape of compute by enabling open industry-wide collaboration around highly flexible enterprise-grade embedded processors and cores.  This ecosystem will provide an opportunity for networking equipment vendors to source and collaborate on high-quality open source cores, and build their platforms around an open and flexible standards-based architecture.  RISC-V, together with P4-enabled switches, will enable new low-latency interconnects required for demanding next-generation wireless infrastructure, including coherent memory-fabrics to enable ultra-low latency shared memory between systems.  Please join us to learn how RISC-V and P4 will change the landscape of compute and enable next-generation system architectures in the telecommunications industry and beyond.